1. Field of the Invention
This invention relates to a semiconductor memory circuit, and more particularly to a static type semiconductor memory circuit.
2. Description of the Prior Art
A semiconductor memory circuit, for example, a static type semiconductor member circuit, basically comprises many memory cells for storing data, word decoders which specify the address of the memory cells arranged in the form of a matrix from the word direction and column decoders which specify the address of the memory cells from the column direction. These word decoders and column decoders are respectively arranged along one side in the vertical direction and one side in the lateral direction of the memory cells, and can read the data stored in the one memory cell specified by the word and column decoders. In practice, the memory cells are divided into two groups, the right memory cell group and the left memory cell group and the word decoders are arranged at the center of the right and left memory cell groups. This arrangement is desirable because if the word decoders were arranged along the vertical direction, the voltage drop between the ends of the polysilicon electrodes extending in the lateral direction becomes very large. Therefore, the word decoders are located at the center of the right and left memory cell groups in order to reduce the voltage drop to a half, and distribute equally the voltage drop to the right and left memory cell groups, thereby improving the memory function.
However, the abovementioned semiconductor memory circuit is inevitably accompanied by disadvantages. The first disadvantage is a high power consumption, and the second disadvantage is that output operation speed cannot be made so high in relation to such high power consumption. This disadvantage results from the following. Namely, a bit current flows to all memory cells storing logic 0 data "L" in the memory cell group selected by the word decoder due to the structure of semiconductor memory circuit regardless of whether the relevant memory cells are also selected in the bit direction or not. Therefore, when the bit current can be reduced by at least a half, it is a considerable step in solving such disadvantage.